/**
 * In earlier version of Verilog ,we used to use 'or' to specify more than one sensitivity list element. 
 * In the case of Verilog 2001, we use comma as shown in the example below.
 * 在Verilog的早期版本中，我们使用'or'来指定多个敏感性列表元素。在Verilog 2001中，我们使用逗号，如下例所示。
 * 
 * We can use the same for edge sensitive code also, as shown in the code below.
 * 我们也可以使用相同的边缘敏感代码，如下面的代码所示。
 */

module comma_edge_example();

reg clk, reset, d;
reg q, q95;

// Verilog 2k example for usage of comma
// Verilog 2k逗号用法示例
always @ (posedge clk, posedge reset)
begin : V2K
  if (reset) q <= 0;
  else q <= d; 
end

// Verilog 95 example for above code
// 以上代码的Verilog 95示例
always @ (posedge clk or posedge reset)
begin : V95
  if (reset) q95 <= 0;
  else q95 <= d; 
end

initial begin
  $monitor ("%g clk=%b reset=%b d=%b q=%b q95=%b", 
    $time, clk, reset, d, q, q95);
  clk = 0;
  reset = 0;
  d = 0;
  #4 reset = 1;
  #4 reset = 0;
  #1 d = 1;
  #10 $finish;
end

initial #1 forever clk = #1 ~clk;
// always #1 clk = ~clk;

endmodule
